H01L27/08- Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind.H01L27/04- Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body.H01L27/02- Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier including integrated passive circuit elements with at least one potential-jump barrier or surface barrier.H01L27/00- Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate.H01L- SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10.Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG Priority to US12/109,976 priority Critical patent/US7964460B2/en Publication of US20080233694A1 publication Critical patent/US20080233694A1/en Priority to US13/109,391 priority patent/US8669154B2/en Application granted granted Critical Publication of US7964460B2 publication Critical patent/US7964460B2/en Priority to US13/846,641 priority patent/US8685814B2/en Priority to US14/194,175 priority patent/US9000531B2/en Status Active legal-status Critical Current Anticipated expiration legal-status Critical Links Original Assignee Infineon Technologies AG Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) ( en Inventor Hong-Jyh Li Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Active Application number US12/109,976 Other versions US20080233694A1
#PMOS VS NMOS TRANSISTOR PDF#
Google Patents Method of manufacturing an NMOS device and a PMOS deviceĭownload PDF Info Publication number US7964460B2 US7964460B2 US12/109,976 US10997608A US7964460B2 US 7964460 B2 US7964460 B2 US 7964460B2 US 10997608 A US10997608 A US 10997608A US 7964460 B2 US7964460 B2 US 7964460B2 Authority US United States Prior art keywords region gate gate dielectric workpiece disposed over Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US7964460B2 - Method of manufacturing an NMOS device and a PMOS device US7964460B2 - Method of manufacturing an NMOS device and a PMOS device
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